The Bi Ra Model GP-IP is a general purpose programmable module that contains an Altera 10K40 FPGA, two tapped delay lines, 256k bytes of static RAM, a 10 MHz crystal oscillator, and two clock receiver discriminators. A 8-pin PROM socket is used to hold a 1Mbit serial PROM that programs the Alters chip after power-up. An 8-bit option switch is available to select various operating options. Implementing various circuit designs using this module only requires plugging in the serial PROM containing the design information needed to configure the Altera gate array.

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Various Designs implementing the GP-IP

The Bi Ra Model IP-177 has eight 16-bit delay timers on board and 40 bits of digital I/O connected to the user connector. Each channel has an associated delay register, an output pulse width register, and a control register. Once triggered, the timers will delay for a variable amount of time determined by the value stored in the delay register before outputting a pulse with a width determined by the value stored in the width register. Parameters that affect all channels are stored in the Master Control Register.

Like the Model IP-177, the GP-IP Clock Generator module design is based from the General Purpose IP module (GP-IP). I/O for the clock generator board includes a TC1k input, an input for 10 MHz signal for backup, an input for 15 Hz backup, 16 pulsed event input trigger signals, and outputs for the encoded clock, status bits to indicate when the 15 Hz and the 10 MHz from the input clock are no longer present. Several test point signals are also available on the IP module’s user connector. A block diagram of the clock generator is given in Figure 1.

Figure 1. GP-IP Based Clock Generator Block Diagram