BiRa Systems

CAMAC Products

MODEL 5909

SIMULTANEOUS SAMPLING 32 CHANNEL TRANSIENT DIGITIZER WITH EXTERNAL MEMORY MODULES UP TO ONE MEGAWORD OF SRAM

FEATURES

GENERAL DESCRIPTION

The Bi Ra Model 5909 is a multi input 12-bit resolution Analog-to-Digital Converter utilized with the Model 59256A (256K) modular memory. This Data Logger system is generally utilized in low frequency multiple sample transient monitoring applications.

ANALOG

The 5909 is a 12-bit resolution Transient Digitizer which contains 32 differential analog channels. Each channel has a dedicated track and hold to allow simultaneous sampling. Samples are stored in separate static memory locations. The Model 5909 offers 12-bit resolution. It has full scale input voltages selectable for bipolar 2.5V, 5.0, 10.0V; 2.56, 5.12, 10.24 and unipolar 5.0V, 10.0; 5.12, 10.24V.

INPUT CHARACTERISTICS
Analog inputs 4,8,16, or32, Direct coupled
Impedance 10K balanced to ground
Bandwidth 0.1db DC to (Determined by resistor terminations)greater than 20KHz
CMRR DC-1KHz 70dB MIN, 1KHz-20KHz 50dB MIN.
Overvoltage Protection +/-100 for short duration pulses.

ACTIVE CHANNELS:

Computer programmable four, eight, sixteen, or thirty-two channels.

SAMPLING RATE:

Sampling is governed by: a group of computer selectable sampling frequencies available from an internal clock or an external input clock.

MAXIMUM SAMPLING RATE:

Maximum sampling rate is calculated as follows: Five microseconds times the number of active channels, plus five microseconds. Maximum sampling rate for four channels is therefore 25 microseconds or 40KHz and approximately 6KHz for 32 channels. (Typical Max. exceeds stated frequencies by greater than 25%.)

SAMPLE RATE CLOCK:

Computer programmable clock speeds are:

40KHz, 20KHz, 10KHz, 5KHz, 1KHz, .5KHz, and .2KHz.

CLOCK AND CHANNEL NUMBER SELECTION:

Available sampling frequencies: No. of active Inputs that sampling frequencies are valid for:
40KHz 4
20KHz 4, 8
10KHz 4, 8, 16
5KHz 4, 8, 16, 32
All slower frequency 4, 8, 16, 32

MEMORY SYSTEM:

The 5909 communicates with modular memories through a rear auxiliary connector and supports up to 1 Megaword with the 59256A (256K) memory. Module interconnection is through the ANSLEY 609-4007 IDC.

OPERATING MODES:

A) Post trigger mode fills all available memory after an event trigger. The CAMAC Crate Controller arms the digitizer. Memory address is reset to zero. The unit awaits the external event trigger. Upon receipt of the event trigger and in conjunction with the sampling clock, the inputs are sampled by the track and hold circuits. A preset number of active input channels are scanned. The Analog-to-Digital Converter sequentially converts the scanned inputs to digital information and stores it in memory. The digitizing continues until the memory is full or the operation is commanded to terminate.

B) Pre-trigger mode allows selectable quantities of data to be retained before and after an event trigger. The entire memory may be filled with new data. After being armed and in conjunction with the sampling clock, the 5909 starts taking and storing measurement continuously. Therefore, only the latest measurements are actually stored in memory at any given time. Upon receipt of an event trigger, the system stores a preselected number of post-event samples in memory.


AUTOMATIC TEST:

The module also contains a self-test circuit which applies a triangular analog signal to all inputs via command. The intent of this mode of operation is to verify functionality.

FUNCTION CODES:

COMMAND Q ACTION
F0 A0 RD1 1 Read Status-Status Register R1-R3(Operating Mode), R4-R5 (Operating State), R6-R10 (Available Memory), R11-R12 (FS Setting), R13-R14 (No. Active Channel), and R15-R18 (Clock Selected).
F0 A1 RD1 1 Read Post Trigger sample count-Contents of Register 1, R1-R20 returned (preset by ARM command) represents number of post-trigger sample blocks (16 word blocks) programmed to be taken.
F0 A2 RD1 1 Read Register R2-Valid Sample Register count R1-R19 indicates number of samples taken for Channel 0. R20=1 if all available memory contains new data.
F2 Ax RD2 1 Read Memory Buffer-Zero for data and Q if not in UNLOAD. IN UNLOAD gates buffer contents on dataway right justified so R1=LSB maintained at 1.24mV/bit (except for +/-10V) with sign extended to 16 bits. Increments memory and loads new data in buffer after read. x in command is determined by A1-A8.Provides means to selectively read every reading of a selected channel utilizing F16 A1 and F2 A0 up to every 16th for F2 A15.
F6 A0 F06 1 Read Module ID-R1 through R12 indicates decimal, 908.
F16 A0 WT1 1 Arm Module-Sets digitizing mode. Required prior to digitizing sequence. Clears EOR and memory address to 0, W1 (Operating Mode), W2-W5 (Digitizing Clock),9 W6-W7 (Active Channels), W8 (Unassigned), and W9-W24 (Post-trigger Sample Count).
F16 A1 WT1 1 Enable Unload-W1-W8 relative address of requested channel data to be transferred to dataway during read. Quantity is added to OLDEST AVAILABLE data for a given channel. W19-W24 channel number 0-31 data desired. Returns Q=0 if request channel was not digitized since the last ARM.
F25 A0 XEQ 1 Set End of Record-Forces EOR flag and status.
F25 A1 XEQ 1 Start Self Test-If module is ARMED, starts test and returns Q=1.
F26 A0 ENB 1 Module Rearm-Same as F16 A0 except previously written W1-W24 data used.
Z+C CZ 0 Clears memory, sets Mode 0, and ignores dataway operation for up to 2 seconds.
X   Valid for all addressed commands.

POWER REQUIREMENTS:

+6 Volts 2175 mA
+24 Volts 430 mA
-24 Volts 920 mA

WEIGHT:

1.25Kg. (2 lb. 12oz.)

ORDERING INFORMATION:

ACCESSORIES:

XX IS THE NUMBER OF MEMORY MODULES +1.


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Bi Ra Systems, Incorporated
2404 Comanche Road NE
Albuquerque, New Mexico 87107

Ph : 505-881-8887
Fax:505-888-0651