The Bi Ra Model 4912R is a single-width CAMAC module capable of controlling up to 15 Model 5907C digitizer modules. The 4912R controller interfaces to the CAMAC dataway and provides up to 128K words of memory addressing to the auxiliary bus. Convert pulses, unload sequences, and channel addressing are initiated through the front panel via ribbon connector.The 4912R must be connected to each digitizer with a front panel ribbon connector and auxiliary bus connector. The starting and sequencing of the controller is accomplished by setting up and arming the 4912R, then sending a trigger command (F25 A2) or trigger pulse to the front panel TRIG IN lemo. When the channel address is 0, all digitizers connected to the controller are enabled to allow analog to digital conversions to begin.
The 4912R controller has internally generated, programmable sample rates of 200Hz to 500KHz that are selectable from the dataway during setup. If an external sample rate clock source is desired, the front panel provides a CLK IN input (SW3 open), or a 2MHz crystal oscillator can be activated (SW3 open, SW4 open, SW5 closed).The 4912R supports single block memory in 8K, 32K, 64K, or 128K words of memory addressing and the desired amount is selected by setting switch 1 and 2 to the proper position. All digitizers connected to the 4912R must use the same sample rate and memory size. Individual digitizers may be set up to use an external remote memory instead of its own. See 5907 manual. For unloading data acquired the 4912R Enable Unload command is issued first to set the starting address of memory and channel address to specify the digitizer memory to be read. Then the Read Memory Buffer command is issued repeatedly to increment through the memory addresses desired.
| COMMAND | Q | ACTION |
|---|---|---|
| F0 A0 RD1 | Read Status Register #1: Mode, State, Amount of Memory, clock Select and source. | |
| F0 A2 RD1 | Read Status Register #2: EOB and EOR | |
| F2 A0 RC1 | Read Memory Buffer. Read data from the next memory location. | |
| F6 A0 F06 | Read Module I.D. Decimal 912. Gates to dataway. | |
| F16 A0 WT1 | 1 | Set Up Module. Sets desired internal clock rate. Q=1 if accepted. |
| F17 A0 WT2 | Enable Unload. Command must be issued before Read Command in order to set starting address of memory to be read, and to set channel address of the digitizer that corresponds to the data to be read. | |
| F25 A0 XEQ | Set "End of Record". | |
| F25 A2 XEQ | Trigger Module from dataway. | |
| F26 A0 ENB | Arm Module. |
| +6 Volts | 570 mA |
|---|
.4kg (14oz.)
Model 4912R Transient Digitizer Controller
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